As the density of semiconductor devices increases, the demands on interconnect layers for connecting the semiconductor devices to each other also increases. Therefore, there is a desire to switch from the traditional aluminum metal interconnects to copper interconnects and from traditional silicon-dioxide-based dielectrics to low-k dielectrics, such as organo-silicate glass (OSG). Semiconductor fabrication processes that work with copper interconnects and newer low-k dielectrics are still needed. As compared to the traditional subtractive plasma dry etching of aluminum, suitable copper etches for a semiconductor fabrication environment are not readily available. To overcome the copper etch problem, damascene processes have been developed.
In a damascene process, the IMD (intrametal dielectric) is formed first. The IMD is then patterned and etched to form a trench for the interconnect line. If connection vias have not already been formed, a dual damascene process may be used. In a dual damascene process, the trench is formed in the IMD and a via is etched in the (interlevel dielectric) ILD for connection to lower interconnect levels. The barrier layer and a copper seed layer are then deposited over the structure. The barrier layer is typically tantalum nitride or some other binary transition metal nitride. The copper layer is then electrochemically deposited using a seed layer over the entire structure. The copper is then chemically-mechanically polished (CMP'd) to remove the copper over the IMD, leaving copper interconnect lines and vias. A metal etch is thereby avoided.
Patterning and etching in a dual damascene process can be problematic due to the necessity of forming both the trench and the via before filling either with copper. Both trench-first and via-first processes are being developed. In a via-first process, the via is patterned and etched followed by the trench patterning. The bottom of the via needs to be protected during the trench etch to prevent etching of the via etch-stop layer. A BARC (bottom-antireflective coating) via fill has been proposed for protecting the bottom of the via during the trench etch. A spin-on organic BARC is often used to reduce substrate reflectivity during resist pattern. This BARC may be used to protect the bottom of the via. Methods for effectively integrating a BARC fill in a dual damascene process without creating additional processing problems are desired. Moreover, as new technologies demand ever smaller critical dimensions (CDs) in semiconductor devices, CD control becomes more important. Semiconductor processes must be controllable so that the small CDs can be reproduced.